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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM6227B/D
1M x 1 Bit Static Random Access Memory
The MCM6227B is a 1,048,576 bit static random-access memory organized as 1,048,576 words of 1 bit. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6227B is each equipped with a chip enable (E) pin. This feature provides reduced system power requirements without degrading access time performance. The MCM6227B is available in 300 mil and 400 mil, 28-lead surface-mount SOJ packages. * * * * * * Single 5 V 10% Power Supply Fast Access Times: 15/17/20/25/35 ns Equal Address and Chip Enable Access Times Input and Output are TTL Compatible Three-State Output Low Power Operation: 115/110/105/100/95 mA Maximum, Active AC
MCM6227B
J PACKAGE 300 MIL SOJ CASE 810B-03
WJ PACKAGE 400 MIL SOJ CASE 810-03
PIN ASSIGNMENT
A A A A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A A A A A A NC* A A A A D E
BLOCK DIAGRAM
A A A A A A A A ROW DECODER MEMORY MATRIX 512 ROWS x 2048 x 1 COLUMNS
A NC A A A A Q W VSS
PIN NAMES
A A . . . . . . . . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . . Write Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable D . . . . . . . . . . . . . . . . . . . . . . . . Data Input Q . . . . . . . . . . . . . . . . . . . . . Data Output NC . . . . . . . . . . . . . . . . . . No Connection VCC . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . Ground *If not used for no connect, then do not exceed voltages of - 0.5 to VCC + 0.5 V. This pin is used for manufacturing diagnostics.
D
INPUT DATA CONTROL
COLUMN I/O COLUMN DECODER
Q
E A W A A A A A A A A A A
REV 3 10/31/96
(c) Motorola, Inc. 1994 MOTOROLA FAST SRAM
MCM6227B 1
TRUTH TABLE
E H L L W X H L Mode Not Selected Read Write I/O Pin High-Z Dout High-Z Cycle -- Read Write Current ISB1, ISB2 ICCA ICCA
H = High, L = Low, X = Don't Care
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to 7.0 - 0.5 to VCC + 0.5 20 1.1 - 10 to + 85 0 to + 70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
Storage Temperature Tstg - 55 to + 150 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns). ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width 20 ns). Symbol VCC VIH VIL Min 4.5 2.2 - 0.5* Max 5.5 VCC +0.3** 0.8 Unit V V V
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH, Vout = 0 to VCC) AC Active Supply Current (Iout = 0 mA, VCC = max) MCM6227B-15: tAVAV = 15 ns MCM6227B-17: tAVAV = 17 ns MCM6227B-20: tAVAV = 20 ns MCM6227B-25: tAVAV = 25 ns MCM6227B-35: tAVAV = 35 ns AC Standby Current (VCC = max, E = VIH, f fmax) MCM6227B-15: tAVAV = 15 ns MCM6227B-17: tAVAV = 17 ns MCM6227B-20: tAVAV = 20 ns MCM6227B-25: tAVAV = 25 ns MCM6227B-35: tAVAV = 35 ns CMOS Standby Current (E VCC - 0.2 V, Vin VSS + 0.2 V or VCC - 0.2 V, VCC = max, f = 0 MHz) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) ISB2 VOL VOH ISB1 -- -- -- -- -- -- -- 2.4 40 35 30 25 20 5 0.4 -- mA V V Symbol Ilkg(I) Ilkg(O) ICCA -- -- -- -- -- 115 110 105 100 95 mA Min -- -- Max 1 1 Unit A A mA
MCM6227B 2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Characteristic Input Capacitance Input and Output Capacitance All Inputs Except Clocks and D, Q E and W D, Q Symbol Cin Cin, Cout Typ 4 5 5 Max 6 8 8 Unit pF pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1a
READ CYCLE TIMING (See Notes 1 and 2)
6227B-15 Parameter Read Cycle Time Address Access Time Enable Access Time Output Hold from Address Change Enable Low to Output Active Enable High to Output High-Z Symbol tAVAV tAVQV tELQV tAXQX tELQX tEHQZ Min 15 -- -- 5 5 -- Max -- 15 15 -- -- 6 6227B-17 Min 17 -- -- 5 5 -- Max -- 17 17 -- -- 7 6227B-20 Min 20 -- -- 5 5 -- Max -- 20 20 -- -- 7 6227B-25 Min 25 -- -- 5 5 -- Max -- 25 25 -- -- 8 6227B-35 Min 35 -- -- 5 5 -- Max -- 35 35 -- -- 8 Unit ns ns ns ns ns ns 5, 6, 7 5, 6, 7 4 Notes 2, 3
NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. At any given voltage and temperature, tEHQZ max is less than tELQX min, both for a given device and from device to device. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E VIL).
TIMING LIMITS
+5V RL = 50 OUTPUT Z0 = 50 VL = 1.5 V OUTPUT 255 5 pF 480 The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
(a)
(b)
Figure 1. AC Test Loads
MOTOROLA FAST SRAM
MCM6227B 3
READ CYCLE 1 (See Notes 1, 2, and 8)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
READ CYCLE 2 (See Note 4)
tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tELQX Q (DATA OUT) HIGH-Z tAVQV tELICCH DATA VALID tEHICCL tEHQZ
ICC SUPPLY CURRENT ISB
MCM6227B 4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
6227B-15 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Data Valid to End of Write Data Hold TIme Write Low to Data High-Z Write High to Output Active Symbol tAVAV tAVWL tAVWH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX Min 15 0 12 12 7 0 -- 5 Max -- -- -- -- -- -- 6 -- 6227B-17 Min 17 0 14 14 8 0 -- 5 Max -- -- -- -- -- -- 7 -- 6227B-20 Min 20 0 15 15 8 0 -- 5 Max -- -- -- -- -- -- 7 -- 6227B-25 Min 25 0 17 17 10 0 -- 5 Max -- -- -- -- -- -- 8 -- 6227B-35 Min 35 0 20 20 11 0 -- 5 Max -- -- -- -- -- -- 8 -- Unit ns ns ns ns ns ns ns ns 4, 5, 6 4, 5, 6 Notes 3
Write Recovery Time tWHAX 0 -- 0 -- 0 -- 0 -- 0 -- ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
WRITE CYCLE 1 (W Controlled See Notes 1 and 2)
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tDVWH DATA VALID tWHQX tWHDX tWHAX
MOTOROLA FAST SRAM
MCM6227B 5
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
6227B-15 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Enable to End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Symbol tAVAV tAVEL tAVEH tELEH, tELWH tWLEH tDVEH tEHDX Min 15 0 12 10 12 7 0 Max -- -- -- -- -- -- -- 6227B-17 Min 17 0 14 11 14 8 0 Max -- -- -- -- -- -- -- 6227B-20 Min 20 0 15 12 15 8 0 Max -- -- -- -- -- -- -- 6227B-25 Min 25 0 17 15 17 10 0 Max -- -- -- -- -- -- -- 6227B-35 Min 35 0 20 20 20 11 0 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 4, 5 Notes 3
Write Recovery Time tEHAX 0 -- 0 -- 0 -- 0 -- 0 -- ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high-impedance state. 5. If E goes high coincident with or before W goes high, the output will remain in a high-impedance state.
WRITE CYCLE 2 (E Controlled See Notes 1 and 2)
tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX Q (DATA OUT) HIGH-Z tELWH tEHAX
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
6227B
XX
XX
XX
Shipping Method (R2 = Tape and Reel, Blank = Rails) Speed (15 = 15 ns, 17 = 17 ns, 20 = 20 ns, 25 = 25 ns, 35 = 35 ns) Package (J = 300 mil SOJ, WJ = 400 mil SOJ)
Full Part Numbers -- MCM6227BJ15 MCM6227BJ17 MCM6227BJ20 MCM6227BJ25 MCM6227BJ35
MCM6227BJ15R2 MCM6227BJ17R2 MCM6227BJ20R2 MCM6227BJ25R2 MCM6227BJ35R2
MCM6227BWJ15 MCM6227BWJ17 MCM6227BWJ20 MCM6227BWJ25 MCM6227BWJ35
MCM6227BWJ15R2 MCM6227BWJ17R2 MCM6227BWJ20R2 MCM6227BWJ25R2 MCM6227BWJ35R2
MCM6227B 6
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
28 LEAD 400 MIL SOJ CASE 810-03
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. DIM A B C D E F G H K L M N P R S MILLIMETERS MIN MAX 18.29 18.54 10.04 10.28 3.75 3.26 0.50 0.39 2.48 2.24 0.81 0.67 1.27 BSC 0.50 -- 1.14 0.89 0.64 BSC 5 0 1.14 0.76 11.30 11.05 9.65 9.15 1.01 0.77 INCHES MIN MAX 0.720 0.730 0.395 0.405 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC -- 0.020 0.035 0.045 0.025 BSC 5 0 0.030 0.045 0.435 0.445 0.360 0.380 0.030 0.040
28 LEAD 300 MIL SOJ CASE 810B-03
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. 5. 810B-01 AND -02 OBSOLETE, NEW STANDARD 810B-03. S MILLIMETERS MIN MAX 18.29 18.54 7.74 7.50 3.75 3.26 0.50 0.39 2.48 2.24 0.81 0.67 1.27 BSC 0.50 -- 1.14 0.89 0.64 BSC 10 0 1.14 0.76 8.64 8.38 6.86 6.60 1.01 0.77 INCHES MIN MAX 0.720 0.730 0.295 0.305 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.020 -- 0.035 0.045 0.025 BSC 10 0 0.030 0.045 0.330 0.340 0.260 0.270 0.030 0.040
F DETAIL Z
28 15
N D 24 PL 0.18 (0.007)
M
1 14
TA
S
-AL G M
H BRK
0.18 (0.007) P -BM
TB
S
E 0.10 (0.004) K DETAIL Z -TSEATING PLANE
C
R 0.25 (0.010)
S
S RAD TB
S
DIM A B C D E F G H K L M N P R S
MOTOROLA FAST SRAM
MCM6227B 7
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MCM6227B 8
MCM6227B/D MOTOROLA FAST SRAM

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